ORSoC -

ORSoC has started a partnership with KNCminer

KNCminer offering first class Bitcoin mining products with high performance.

In our partnership ORSoC will be responsible for product development, including design, production and testing.

Our technical expertise together with excellent vendor partnership we feel confident we quickly can design and produce an affordable high performance mining product.

More information about KNCminer available at www.kncminer.com

Questions regarding these products are handled by KNCminer.

ORSoC proudly presents a new System on Module specially designed for products require processing systems combined with programmable logic.

This module is a well-designed system consisting of eg processor and a powerful FPGA at low cost, enabling time and cost-effective product development

ORSoC "ARM SoC SO-DIMM" module

The module is built with SO-DIMM form factor, making it easy to tailor the product with appropriate external interfaces and connectors.

The module includes a complete processor system tightly coupled together with a 22K LUT Altera FPGA, providing flexibility and support for a wide range of application, for example:

• Distributed IO systems
• Industrial controllers
• Ethernet switching systems
• Data capturing systems
• Supervision/Monitoring systems
• Cryptography systems

More information about this product

Please come and visit us in our both. We will be pleased to see you there.

The conference is taking place at ÅF, Frösundaleden 2A, Solna (Sweden), September 4th 2012

Välkommen till ORSoCs frukostseminarie om OpenCores och OpenRISC den 27:e mars i Göteborg!

Vad betalar du för egentligen när du köper in RTL IPn? Hur stort är open source för ASIC/FPGA?

Under seminariet bjuder vi på frukost och  vi kommer även att lotta ut utvecklingskortet vi använt oss av. (http://orsoc.se/altera-fpga-development-board)

Vi som kommer att hålla i seminariet är Olof Kindgren och Daniel Eriksson.

Seminariet kommer att hållas den 27:e mars kl 8:00 och pågår i ca 45 minuter.
Plats för presentationen är lokalen Marsstrand i Södra Porten på Flöjelbergsgatan 1C i Mölndal. Närmsta busshållplats är Bergfotsgatan. Mer information om hur man hittar finns här.

Skicka en anmälan till frukostseminarie@orsoc.se senast den 20:e mars, med kontaktinformation samt  information om vilket företag ni jobbar för och vad ni har för roll där.

Varma välkomna!

ORSoC is recognized by Deloitte as one of the 50 fastes growing technology companies in Sweden and is in the list of top 500 fastest-growing technology companies across EMEA.

The programme recognises the 50 fastes growing companies in Sweden and the 500 fastest-growing technology companies across Europe, the Middle East and Africa (EMEA), based on percentage revenue growth over the last five years.

With version 3.1 of Linux, the OpenRISC processor is now one of the few open source processor architectures that are officially supported.

This mile stone is very important and gives many nice features. We are sure this will even further accelerate the usage of the OpenRISC processor in embedded products.

Xing has an extensive experience from both FPGA and ASIC design and verification. Xing has also good knowledge in UVM (verification metadology).

The conference is taking place in Stockholmsmässan, Stockholm Sweden the 4-5^th of October 2011

ORSoC will present:
“Hardware IPs as open source – the future of SoC design and FPGA / ASIC development”

Right now there is running a number of interesting FPGA projects based on the open source processor “OpenRISC12000” from OpenCores.org and the associated development platform from ORSoC. Some of the key benefits of using open source Ips for SoC design are:

• Minimize “end of life problems”
• License “freedom” regarding both licensing costs and lock-in effects.
• Full access to source code means faster development, debugging and verification.
• Improved copy protection – especially when it comes to using an embedded processor in combination with internal hardware accelerator.

Besides the obvious benefits (some stated above) the major driving force for so many projects in based on open source techology starts right now is that the tool chain and the unique verification environments is state of the art (bleeding edge). In many cases far ahead of the “commercial” options. The OpenRISC1200 processor is now ported to the latest Linux version 2.6.38. Work is continuing on 2.6.39. Even this is ahead of most competitors.

Our presentation will provide an overview of open source within HW.

• What type of IPs available?
• What is / happens on OpenCores – world’s largest site/community for open source development?
• What are the major benefits of open source HW (direct and indirect)?
• What tools and environments are available?
• Who uses this technology today?

Many developers have for a long time understood the great advantages of open source technology. Since about a year back all puzzle pieces are in place, i.e. predesigned platforms, bleeding edge tool chains and unique verification environment. This has opened up for anyone who wants to base their products on OpenCores technology to effectively pursue development projects.

Presenter Johan Rilegård

Nikos is working in the field of FPGA design and has also experience from verification.

For more information about available resources, please contact Johan Rilegård: +46 70 824 80 30

Per has been working with FPGA development of more than 15 years and have extensive knowledge in field. We are glad to have Per in our team.

For more information about available resources, please contact Johan Rilegård: +46 70 824 80 30

Please come and visit us in our both and/or listen to our presentation (Howto design a complex efficient SoC design based on OpenRISC processor)

The conference is taking place in Electrum Kista, Stockholm Sweden the 13^th of September 2011.

Yann has exceptional skills within many different areas, that covers from RTL design and verification all the way up to SW design.

For more information about available resources, please contact Johan Rilegård: +46 70 824 80 30

OpenCores – creating the worlds first open-source OpenRISC processor ASIC

OpenCores starts donation site – to creating the worlds first open-source OpenRISC ASIC.

The 29th of April OpenCores released a donation site to collect funding for an open-source OpenRISC ASIC. The goal is to create a “super-low-cost” SoC ASIC component based on the OpenRISC processor.

We would like to challenge the industry with a flat-price ASIC regardless of volumes. The price-level will be set accordingly based on the accumulated annual volume, meaning that all will benefit if the volumes goes up, not only buyers with high volumes. This will be a joint-venture, trying to increase the overall volumes which will lead to even lower unit-costs. This also means that smaller companies can compete with larger companies on fair condition and get the same price for the ASIC.

The plan is to develop a complete SoC design (System-on-Chip) and implement it into an ASIC-component, and then offer it back to the OpenCores community as a “super-low-cost” OR1200 processor based SoC ASIC-component, which can be used to develop commercial products without any restrictions or royalties. A development board will also be developed using this OpenRISC-ASIC.

This product will be perfect for many industries and very suitable for develop complete cost-efficient Linux based products.

For more information and donations, please visit: www.opencores.org/donation

ORSoC has employed Daniel Eriksson to our Göteborg office. Daniel has an ASIC background and worked with both design and verification. Daniel has worked with IP design/integration and DSP functionality. With his experience and positive personality, Daniel will be a great addition to our team.

For more information about available resources, please contact Johan Rilegård: +46 70 824 80 30

Avnet Memec, Lattice Semiconductor and ORSoC, are happy to invite you to a seminar to learn more about the benefits of Open Source IP for rapid hardware development, debug and verification of hardware IP including the OpenRISC Processor platform. Further Lattice will introduce the new MachXO2, the low cost, low power, small standalone FPGA platform with hard SPI, I2C and User Flash blocks, making it the ideal platform for integrating open source IPs.

2011-04-12: Västerås – AROS Congress Center
2011-04-13: Linköping – Collegium, Mjärdevi

For registration, please click here.

Welcome!

Agenda
Registration from 14.30 (Seminar start 15.00)
Avnet Memec
• Welcome and Introduction
ORSoC
• ORSoC introduction
• OpenCores Overview
• OpenRISC Processor Platform Overview
• Open Source Hardware statements “It’s the only way forward”
Lattice
• Lattice Brief Overview
• uP Peripheral & Interface Common Applications
• MachXO2 and Applications
• Lattice Open Source Peripherals and Reference Designs
• Minimising Power with MachXO2
• Lattice Diamond Software- brief intro and MachXO2 Pico Board SOC demo

Seminar end 17.30
17.30 – 19.00 Light Food & Drinks

For more information, please contact Johan Rilegård, +46 70 824 8030

ORSoC has employed Stefan Eriksson to our Stockholm office. Stefan has +20 years experience in the field of FPGA development and firmware design. Stefan also have extensive experience from verification and Software design. Stefan has worked with many different customers with different products and applications. We are very glad to have Stafen in our team.

For more information about available resources, please contact
Johan Rilegård: +46 70 824 80 30

ORSoC, representing OpenCores, were invited to the “Electronics For You”-expo (EFY-expo) as Key-Note speaker, to present our view on open-source hardware development. We did a presentation that covered the OpenCores ecosystem and why we strongly believe that “Open Source hardware IP development is the only efficient method going forward”. It was truly a great exhibition with allot of visitors and exhibitors, and there was a strong feeling of innovation talking with engineers and exhibitors and we were impressed by their ideas/knowledge and motivation. We encourage all OpenCores users to visit EFY Expo next year, you will not regret it!

Below are some information about the EFY-expo (www.efyexpo.com):

Electronics For You Expo 2011 is a first-of-its-kind electronics event, from the leading publication serving South Asia’s electronics industry. With the sole aim to accelerate the growth of the electronics industry in India, the expo focuses not only on “components” and “manufacturing equipments” but on the entire eco-system.

In order to build a comprehensive platform for the electronics industry, EFY Expo has everything that an electronics event should provide–starting from innovation (new technology), product design, manufacturing and lastly product sales. The ambit of visitors range from innovators (developers of new technology), design engineers, manufacturers and B2B buyers.

The EFY Group
Over the last 42 years, the EFY group has become synonymous with cutting-edge technology. Today, this renowned media group is spread across 8 locations catering to the intellectual needs of a diverse readership across India and abroad.

Starting with its flagship publication Electronics For You, South Asia’a most popular electronics magazine, the group now offers a bouquet of specialized publications to answer the needs of a technology-hungry nation. The Electronics For You magazine, symbolizing the company’s vision, is the source of enlightenment for an elite electronics fraternity, in India and abroad. Surprisingly, the appeal of the subsequent publications – Linux For You, BenefIT, Facts for You and Electronics Bazaar, spilled much beyond the targeted audience – penetrating non-technical readership with rich content and easy-on-the-eye design.

The group also publishes directories and books and is behind several leading technological events. Recently, it also launched web-portals, including Electronicsforu.com, EFYTimes.com, BPOTimes.com and linuxforu.com, which have become leaders in their respective categories.

The EFY Group has also been producing some elite events, some of which include: EFY Awards, EFY Summit, Open Source India (aka LinuxAsia), and EduTech

ORSoC expands, and has moved the Stockholm office to new and bigger premises. Our new office is located in centre of Stockholm

Address
Regeringsgatan 111
SE-111 39 Stockholm
Sweden

You are always welcome to visit us.

ORSoC has employed Martin Wasielewski to our Stockholm office. Martin has +10 years experience in the field of FPGA/ASIC development. Martin has also worked with design architecture issues and hardware systemisation. We are very glad to have Martin in our team.

For more information about available resources, please contact
Johan Rilegård: +46 70 824 80 30

ORSoC has employed Olof Kindgren. Olof is a very skilled FPGA & ASIC developer with many years experience. Olof is located in Gothenburg and will even further improve our presents in the west regions of Sweden. We are very glad to have Olof in our team.

For more information about available resources, please contact Johan Rilegård: +46 70 824 80 30

ORSoC has employed Tor Caesar – a senior FPGA & ASIC developer who has worked within this technical field over 20 years. Tor has worked with products targeted for several different industries and applications, with focus on the telecom sector. With his unique expert knowledge and extensive experience within verification (Specman), Tor has a perfect profile for our customer looking for expert services within FPGA/ASIC development. We are very glad to have Tor in our team.

For more information about available resources, please contact Johan Rilegård: +46 70 824 80 30

We will help our customer to retargeting a big SoC design from a Xilinx FPGA into an Altera device, for further conversion into a gate array ASIC. ORsoC will do all the work of this conversion, including:

• Conversion of the existing Xilinx VHDL design to an Altera FPGA.
• Modification of technology specific parts of the current design (memory, I/O, etc)
• Frontend design (modification of RTL design for top level, I/O ring design)
• Backend design (synthesis, placement, routing, layout, timing)
• Verification
• Project management

The project has a very thigh time schedule and ORSoC has undertaken the whole responsibility.
We are sure this will be a successful project. ORSoC has huge expertise and experience from this kind of work from over 30 FPGA/ASIC conversions.

For more information, please contact Johan Rilegård: +46 70 824 80 30

ORSoC continue growing and increase our team with even more senior resources within FPGA and ASIC design, by employing Krister Karlsson. With over 15 years in the ASIC business, Krister has deep skills and extensive experience in ASIC and DSP development and has developed products targeting several industries, i.e. Chip architecture for network processors, Multiprocessor architectures with application specific DSP, Processor based digital systems for multimedia applications. We are very glad to have Krister in our team.

For more information about available resources, please contact Johan Rilegård: +46 70 824 80 30

ORSoC has designed a development kit for the OpenRISC processor. This kit enables easy access to the OpenRISC platform and gives the designer a fast start.

The development kit includes the following:

• FPGA (CPU) board: The board is shipped with a pre-defined System on Chip design and includes everything to have a CPU system up and running in no time.
• I/O board: This is a companion board to the FPGA board. The boards may be mounted together via fixed-connectors. The I/O board contains several IOs useful for development of many different products/applications i.e. Ethernet, USB, Audio, GPIO, GPs, etc.
• JTAG-USB debugger: The USB to JTAG debugger is aimed at debugging OpenRISC based systems. One or more OpenRISC processors can be controlled over a JTAG interface by easy connection to a USB host. A local proxy server handles the USB connection and offers a TCP connection to a software debugger.
• VMware-image for easy start, including tool-chain and simulation.

More information is available at the Development Kit page.
–”Development Kit” page–

OpenCores.org

We are very glad to finally present the new website of OpenCores (www.opencores.org). During the last couple of months ORSoC (maintainer of OpenCores) has completely re-designed the OpenCores website primarily concerning the technology/platform but also including some layout upgrades. The new platform provides much greater flexibility and enables us to continuously add new features.

Marcus Erlandsson, CTO at ORSoC has been responsible for the upgrade work and describes the news:
The first thing you will notice when visiting the new OpenCores is a new design and logo, but soon you realize that the big improvements are within the services supported by OpenCores, they include:
- The CVS has been replaced with SVN (Subversion is a more modern/better revision control system).
- The Forum has been replaced giving a better overview making it easier to follow the discussions within different threads.
- Statistic improvements – we can now present much better statistical information from all the activities within the community. This includes real time statistics of the overall visitors/users experience as well as statistics for all projects available at OpenCores.

OpenCores is continually growing; more and more companies and engineers visit the site and use the cores as well as discussing design and verification solutions at the forum. Therefore this update was timely and we are very glad to now have a platform which can support all the users and also handle all the future services we will add to the site/community.
The work load to build the new site has been huge, due to the large number of users together with over 600 projects in the repository. Now we have released the new site we will continue to add more functionality that will make it even easier for engineers to develop and distribute open source hardware IP cores on OpenCores.

We hope all users, advertisers and partners will be pleased with the updated version of site and that we soon will be back with more news regarding OpenCores and the services attached to it, says Johan Rilegård CEO at ORSoC.
Enjoy, OpenCores and ORSoC

ORSoC has designed a companion board to the FPGA development board. The boards may be mounted together via fixed-connectors. Intended use is to build Ethernet connected products.

The board has the following functions:

four independent Fast Ethernet ports with RJ45 connectors
serial port with PPS input to be used with GPS receiver
two independent USB host with USB type A connectors
AC’97 compatible audio codec with mic, line in and line out. 3.5mm jack
SD / SDIO connector
4 analog in channels
8 general purpose digital IO
high intensity RGB LED
RC5 compatible IR receiver
The board is 100×100 mm and is supplied from the USB port on your computer or from a USB hub.

More information is available at the I/O board page. “I/O board” page–

ORSoC increase our resources within FPGA and ASIC development, by employing Magnus Anehem. With over 15 years in the ASIC business, Magnus has deep skills and extensive experience in FPGA- and ASIC development. Magnus has mainly worked in projects targeting the telecom industries – including Bluetooth communication and application processor ASIC’s for mobile phones. We are very glad to have Magnus in our team.

For more information about available resources, please contact Johan Rilegård: +46 70 824 80 30

With the background of strong personal cooperation in the past, ORSoC and AsiusTech have decided to form an official partnership combining open source IP technology (from OpenCores) with cost optimization to create a cost effective design technology service.

The expertise within ORSoC and AsiusTech complement each other extremely well. ORSoC has unique expertise within SoC design, including FPGA and ASIC development, based on open source IP cores. AsiusTech has extensive experience in the area of product cost optimization.

ORSoC is established as the number one company working with open source IP cores in FPGA and ASIC design, which gives huge benefits during the entire product life cycle – cost, life time, vendor independency, etc.

AsiusTech will contribute with its expertise in cost optimization processes and strong experience of analysis, design and manufacturing of electronics products.

The partnership is aimed at demonstrating the joint forces of the companies to the market and also enables effective project resources to be allocated for our customers.

â€Å�There is a huge interest of using open source alternatives right now. Cost reduction is one important aspect, but even more important is the independence of specific components/vendors to assure the cost optimization during the entire product life cycle. Together with AsiusTech we can offer the customer a wider scope and optimize the total product cost and the process for manufacturing. This partnership is expected to result in a very positive outcome for our customers”, says Johan Rilegård, ORSoC.

When looking for cost effective ASIC & FPGA technologies, we find the cooperation with ORSoC to be an outstanding partnership for us. We expect that our customers want the increased vendor independency, legacy CPU support for processors near end-of-life and short implementation time”, says Håkan Dahlbom, AsiusTech.

About AsiusTech (www.asiustech.com)
AsiusTech has a long experience of Value Engineering from within one of the major EMS companies in the world. The company offers an electronics design portfolio with product cost optimization as a specialist service. With a background ranging from high volume products and cost reduction studies, to everything from telecom infrastructure and consumer products, AsiusTech help customers to increase or maintain their margins.

For more information, please contact:
Johan Rilegård, CEO ORSoC at +46 70 824 80 30

OpenCores can now proudly announce that we have more than 20,000 registered users. This makes OpenCores the largest community of its kind. The OpenCores website, www.opencores.org, is regularly visited by around 70,000 engineers every month with every one helping to contribute to the development and verification of the new and existing IP cores.

We are extremely proud and excited about the great interest shown for open source hardware IP cores.
The number of newly registered users is continuously increasing by approximately 200 users per day. This means we will have over 50,000 registered users within the next 6 months. This gives OpenCores a unique possibility to generate statistics which will be used to further increase the quality of the IP-cores.

It’s very interesting to see the mix of users within OpenCores. There are FPGA and ASIC developers with many years of experience as well as users from all the big universities. It is quiet fun to present the number of years of experience that are visiting OpenCores every month. If we summarize the experience from all visitors of one month we see that OpenCores is visited by: ~236 000 years experience of FPGA development, ~112 000 years experience of ASIC development ~147 000 years experience of Verification

During the summer OpenCores began developing a new website which will give us the possibility to add many new features. The site will be launched sometime in November and will, from the start, be quite similar to the existing site. The exception being the forum which has had a facelift to improve functionality. This improved functionality will allow us to present improved statics in a more automated format.

OpenCores:
OpenCores is the world’s largest site/community focusing on open source hardware IP cores development. OpenCores source over 550 different IP cores, including processors, peripherals, crypto cores, etc. OpenCores was established back in 1999 and during the last few years the cores have become extremely popular among both big and small companies, thanks to its very clear advantages. OpenCores is owned and maintained by ORSoC, Swedish design house experts in SoC development based on OpenCores technology.

For more information, please contact Johan Rilegård at +46 70 824 80 30

In the August edition of Elektroniktidningen (one of the biggest Nordic magazines within the electronic business) had a big article about ORSoC and OpenCores. Please read the article here.
You can also read the whole magazine here.
Enjoy!

ORSoC will attend to the FPGAworld conference. The conference will take place at Electrum Kista in Stockholm Sweden on September 11 and at Ideon Lund on September 9.
ORSoC will present 3 different presentations.

1) Industrial presentation covering the evaluation of open source within hardware. Using open source cores within SoC design has become very popular the last couple of year and we will during the present discuss the key component behind this highly increased interest.

2) Product presentation EDA-tool. By using ORSoC custom developed EDA-tool (called ISoC) we can put together a SoC design in a very short time. We will during 30 minutes show you this tool and put together a real design.

3) Product presentation eASIC: We will present eASIC’s Nextreme Series which is a new generation of ASIC devices with zero mask charge, that dramatically reduce the cost and risk of doing ASIC design.
Please visit the FPGAworld website (www.fpgaworld.com/conference) to check out the presentation program and registration (the conference and exhibition free).
In Stockholm we will also have a both in the exhibition hall. We look forward to meet you there. /The ORSoC team.

Nextreme-2 is a family of zero mask-charge NEW ASIC devices, manufactured on a 45nm CMOS process, and built using eASIC’s patented single-via customization technology. The Nextreme-2 family provides ASIC-like performance, power and low unit-cost combined with FPGA-like design flow and rapid delivery of devices.

Nextreme-2 is built on a breakthrough configurable fabric which combines efficient Look-Up-Table (LUT) based logic with single via-layer customized interconnect. Nextreme-2 delivers many enhancements and advantages for designers considering standard cell ASICs, FPGAs and ASSPs. More information is available at the –”eASIC” page–

OpenCores is pleased to announce the release of a solution aimed at lowering the technical threshold of development with the open-source OpenRISC processor.

There will always be barriers to overcome when changing to a different processor architecture. OpenCores now offers its flagship LGPL licensed 32-bit RISC processor along with a pre-configured design environment to make these problems easier to solve. Using a virtual machine pre-configured with the necessary tools, it is now even simpler to start integrating proprietary IP, or license-fee free IP from OpenCores, with the world’s most used open-source processor, the OpenRISC 1200.

OpenCores has made available a “Virtual Ubuntu Linux” installation which installs and configures a VMWare virtual machine. It includes all of the tools necessary to start hardware and software development on a OpenRISC platform.

It provides an OpenRISC SoC reference design along with the following development tools:

Icarus Verilog simulator
GTKWave waveform viewer
Software tool-chain based on gcc-4.2.2 with uClibc-0.9.29
Support for Busybox-1.7.5 and Linux-2.6.19
The OpenRISC architectural simulator
This package provides simplicity, ease of use, and is a great leap forward for developers who decide to base their designs on OpenCores IP.
This release is available at: http://www.opencores.org/projects.cgi/web/or1k/vmware_image
For further information, please contact Marcus erlandsson by email: marcus.erlandsson[at]orsoc.se or by phone: +46 70 824 80 33.

A huge amount of new projects have started at OpenCores.org during the last 9 month, from about 400 projects in mid 2007 up to over 500 projects today! The same positive trend is shown in the number visitors to the site.

Among the new projects there seams to be some really interested ones which probably will be highly downloaded and used.

OpenCores has started to improve the site with new features/functionality for the purpose of increase the statistics and feedback from users of different IPs. This is important in our work of supporting the world with well-developed and well verified open source IPs with. Allot of feedback has come into the community and (more or less) everyone see the positive outcome from the improvement. – If everything goes as planed we will be able to present more positive news related to new functions within shortly. Our mission is to support all developers and users of open source IPs with the best possible community for theirs projects.

OpenCores is the world’s largest site/community for development of hardware IPs as open source. The site holds all the IPs and makes them available for everyone to download, use and improve. OpenCores is also a source of information and forums related to IP- & SoC-development.

ORSoC got many request for design services. The major part of our new projects includes designs based on OpenCores IPs. ORSoC continue to work with our existing customers, but have during the last nine month extended our customer base with a number of new, very interesting, customers. The customers act within different industries and they are all developing complex products in extremely competitive markets.

ORSoC is seeking more strong candidates who are experienced in FPGA or ASIC design. Please check out the current vacation page for more details.
–”Current vacancies” page–

ORC32-1208 is an OpenRISC based System-on-Chip implementation. The design suits into many different applications. It is a highly integrated design with a large number of built-in peripherals. More information about the product, including datasheet is available at the ASSP page.

A huge amount of new projects have started at OpenCores during the last 4 month, from about 400 projects up to 469 projects today! The same positive trend is shown in the number of registered users. Among the new projects there seams to be some really interested ones which probably will be highly downloaded and used.

ORSoC has designed a development board for the OpenRISC processor. This board enables easy access to the OpenRISC platform and gives the designer a fast start. The board includes everything to have a CPU system up and running in no time. More information about the product, including datasheet is available at the FPGA Development board page.
–”FPGA Development board” page–

From the 1st of November opencores (www.opencores.org) will be maintained by ORSoC.  For a long period of time ORSoC has worked closely to OpenCores, both with the community and with development of the technology.  The great benefits of open source IPs have been clearly proven in several projects.  There has also been an explosive development in the interest and use of the technology during the last couple of years.

The great interest of OpenCores proves the importance of the site and its philosophy to develop and provide the technology-world with free, open source hardware IPs. To ensure the continuing growth of the site/community ORSoC has decided to accept the mission to maintain and develop OpenCores.

ORSoC will continue to develop and improve OpenCores. We will dedicate resources to work with the site/community which will ensure that the development of IPs will ramp up and the quality of projects and verification will become even higher. In the long term we will also improve the web-site, to make sure it will offer even more services and make it easier for all the skilled engineers to work with IPs at the OpenCores.

ORSoC would like to see cooperation with different companies to create a turbo effect regarding the IP development. We believe there are many companies out there with in-house developed IPs – IPs that is not customer specific and which not is unique for the specific company. If these IPs are placed at OpenCores the IPs will continue to develop and they will be well verified.

ORSoC will also offer companies the possibility to advertise at opencores.org. This will provide an income to enable the site to develop and expand. Opencores.org is visited by millions of engineers from all over the world. Therefore the possibility to advertise at the site is mainly aimed for international companies. We believe that opencores.org is the best available marketplace for offering products/tools/services at the electronic development market.

We have the vision of continued development and improvement of OpenCores  the worlds largest site/community within open source hardware IPs. We hope that all developers and users will continue to contribute to the future of OpenCores.

For more information, please contact Johan Rilegård at +46 70 824 80 30.

ORSoC is looking for talented, new co-workers. Please feel free to e-mail your application.
Job Openings:

• ASIC developer, both with design- and verification expertise. Experience from Specman is positive. Location: Stockholm
• FPGA developer, with deep knowledge and experience in VHDL/Verilog based SoC designs. Location: Stockholm and Västerås.

Please observe that there is an absolute requirement that you speak fluent Swedish and English. For more information and to apply, please contact Johan Rilegård by email: johan.rilegard[at]orsoc.se or by phone: +46 70 824 80 30.

W e can gladly announce that Sven-Åke Andersson joined the ORSoC team. Sven has deep skills and extensive experience in FPGA- and ASIC development from over 30 years in the business. Sven is also well known from his blog “FPGA from scratch” www.fpgafromscratch.com – a very educating on-going tutorial of how to design with FPGAs from the ground up. We are very happy to have Sven in our team.

ORSoC continues looking for skilled and experienced FPGA- and ASIC developers. Since we focus on expert services within this market it is important that you have deep skills and experience within the area. If you like to work in fast growing company with skilled people please contact us.
For further information please contact Johan Rilegård (+46 70 824 80 30)