The OpenRISC platform is a open-source processor platform that provides many important advantages compared to other commercial solutions. The platform is built around the worlds only LGPL-licensed processor, the OpenRISC 32-bit processor developed at OpenCores.org
The platform offers the ability to create a complete System-On-a-Chip design (SoC design) based on open-source IP-cores, which enable the following advantages:
- Cost efficient solution:
No license costs is maybe the first benefit that comes to mind, but there are many more cost-related benefits that are connected with this platform. Some of these cost-benefits is coming from the advantages described below. - No “end of life” problems:
Open-source code in combination with that the source code is developed with a synchronous methodology, enables the option to easily convert/port the functionality to other FPGA/ASIC and make it allot easier for companies to guarantee that they can continue to support older products. - Technology independent:
Many suppliers provide free IP-cores which sometimes look very appealing, however these IP-cores are only allowed to be used in a specific vendor technology. This makes it impossible to switch to another technology and it also provides slim chances to reduce the component price during the annual price negotiation, since the supplier knows that it requires a lot of work to switch to a competitors and use their IP-cores instead. - Reusable and flexible platform:
Open-source enables companies to unlimited access to reuse the code and modify or add functionality to it. - Faster time to market:
Open-source gives full access into all hardware functionality, decreasing both the actual development cycle and also verification/debugging cycle. A function (IP cores) that is well used in the open-source community is often more well verified then a commercial IP core, which also help companies staying away from long-debugging lead-times from a commercial IP-core supplier. - Full access to source-code:
Enable the engineers to fully understand all functions within a design, which then often leads to that the engineers come up with new solutions on how to improve functionality, or making an existing function more efficient based on the products actual requirement. - Extremely powerful debugging/verification solutions:
Open-source Verilog code enable the engineers to use a powerful tool called Verilator. Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Verilator together with other open-source debugging tools allow endless debugging/verification possibilities, which is extremely important to achieve fast “time-to-market”.
The platform is based on the one or multiple OpenRISC (OR1200) processors, with selected peripheral IP-cores and with appropriate hardware-accelerator. A strength with this platform is the possibility to partition the SoC design so that it uses the hardware in an optimum way, as a result of this, it’s common that the overall clock frequency can actually be decreased and still deliver increased system-performance.
Extensive debugging methods
The OpenRISC-platform also offers an extensive debugging/verification solutions, enabling faster development cycle and heavily reduced debugging/verification cycle. These methods can both be used verifying the OpenRISC processor as well as verifying a whole SoC design. It also makes debugging allow more efficient with offering four different parallel debugging/verification methods/tools with one unified interface (GDB). The picture below show these four methods:
These methods are:
- Target debugging/verification:
Allow the test-software to be executed on “real” hardware (FPGA/ASIC) using a USB-to-JTAG-debug-cable. GDB has access to both the internal OpenRISC processor and all other modules that are connected on the internal wishbone-bus. - RTL simulator debugging/verification:
Running the same test-software as above but connecting GDB to an RTL-simulator (Icarus, Modelsim, Silos). - Cycle-accurate-C-model simulation:
Running the same test-software as above but connecting GDB to the Verilator-simulator (fast cycle-accurate Verilog simulator using C++/SystemC). - Architecture C-model simulation:
Running the same test-software as above but connecting GDB to the or1ksim (OpenRISC Archtecture simulator).
Bleeding edge toolchain
The platform is using the latest versions of GNU tools/libraries and Linux, which is important in order to get maximum performance out of a system, and to get the latest features.
- GCC 4.5.1
- Binutils 2.20.1
- Newlib 1.18.0
- uClibc 0.9.29
- GDB 7.2 Debugger
- Architectural Simulator (or1ksim)
- Linux 2.6.39
- Busybox 1.7.5
- ORPSoC (Regression test SoC)
- ORPmon (Bootloader)
Summary:
By building products using an embedded processor platform based on “true” open-source, enable so many important advantages that will force product developing companies to adopt this technology in order to stay competitive. Complexity of todays standard communication interfaces and processors makes it impossible for a individual company to fund the whole verification, the open-source method is the only solution to this problem. ORSoC are the world’s most experienced company developing advanced SoC-designs based on this open-source technology.
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